Delivering low gate charge and resistance for fast switching transistors
A power MOSFET is a specific type of metal–oxide–semiconductor field-effect transistor (MOSFET) designed to handle significant power levels. Compared to the other power semiconductor devices, such as an insulated-gate bipolar transistor (IGBT) or a thyristor, its main advantages are high.
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N-channel MOSFET transistor
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P-channel MOSFET transistor
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MOSFET technical articles
| Title | Description |
|---|---|
| What does a “lead-free” power MOSFET really mean? | Learn about the nuances in the termninology 'lead free' and what you should actually be looking for. |
| Choosing the right SOA for your design: discrete FETs vs. power blocks | Learn the differences in how TI specifies SOA for single, discrete FETs vs. integrated power blocks. |
| FemtoFET™ MOSFETs: small as sand but it’s all about that pitch | Learn about the key benefits of our small FemtoFET™ MOSFETs. |
| Improve the performance of your power tool design with power blocks | Learn how a MOSFET power block helps to achieve a more reliable, smaller-sized, efficient and cost-competitive system solution. |
| MOSFET pair the size of a flake of pepper? | Learn how ultra-thin Power Block II devices allow products to become dense, while consuming less power and dissipating less heat. |
| Selecting the right power MOSFET/power block package for your application | Learn about package thermal capability and power dissipation in TI MOSFET and power block packages. |
| What’s not in the power MOSFET data sheet, part 1: temperature dependency | Learn about what is in a MOSFET data sheet and more importantly, what's not. |
| See all technical documents | |
Task #2: Use a Standard SPICE Parasitic PMOS Model for Gate Capacitances
It turns out that the gate capacitances of an N-channel power MOSFET can be accurately modeled, in a physically correct manner, by adding a parasitic P-channel type device to the usual N-channel SPICE model. I know this seems counter-intuitive (and I've got several anecdotes about 'experts' who told me I didn't know what I was talking about re this!) but please just 'accept it as an assertion' for now. I'll add further explanation in the future. This concept is explained in some detail in one of my ancient papers: 'An Accurate Model For Power DMOSFET's Including Interelectrode Capacitances,' Scott, R. S.; Franz, G. A.; Johnson, J. L., IEEE Transactions on Power Electronics, vol. 6, no. 2, April 1991.
But the SPICE model I developed way back in 1990 or so was based on an incredibly primitive SPICE MOSFET model for the parasitic PMOS device (the reason for using that highly limited SPICE model is another story which I may add in the future). Nowadays, or probably even then, I am sure I could have chosen a more modern and appropriate MOSFET model for the parasitic device that would yield MUCH, MUCH more realistic capacitances. I need to investigate this further. Quite a bit of work involved since I haven't concerned myself with MOS modeling for 20 years or so.
But I am certain that using a more modern SPICE model will correct most of the inaccuracies of my old model. Please stay tuned!
Update 7/3/2014 (and a little-too-much history):
Well, I'm NOT SO CERTAIN NOW! For quite a while I've assumed that a more modern, but still simple, MOS Spice model would be able to fit the capacitance characteristics of a power MOSFET better than what I used back in 1990.
Because it has smooth capacitance vs. voltage characteristics I thought a good candidate model would be the widely-used EKV model - but I never examined it in detail. A few weeks ago I made an effort to see if this model would indeed 'do the job'. There are papers on the internet that describe their capacitance formulas in detail and I looked at some. To my horror, I found that the EKV model incorporates an approximation that also plagued my 1990 model. This has to do with the voltage dependence of the bulk depletion charge capacitance, which IN THE MODEL has a dependence inversely proportional to the square root of a bias voltage term.
Back then I found that I needed to slightly modify the power of this voltage term in the denominator from 0.5 (a square root) to something a bit smaller (maybe 0.4) in order to realistically fit my measured data. This was caused by a geometrical effect similar to the well-known formula for the depletion capacitance of a typical junction. The usual junction capacitance formula includes a voltage term in the denominator that is raised to a power of 0.5 or somewhat higher. The higher value adjusts the model for the geometrical effects of realistic junction curvature.
The way I solved this issue in 1990 was that I called up the authors of the simulator I was using (HSPICE from MetaSoftware) and asked them to add a parameter to their simplest MOS model that would allow me to change the (fixed) power from 0.5 to a slightly lower number. These were the famous technologists Shawn and Kim Hailey. They said OK and I didn't expect to ever hear from them again. But a couple of weeks later my boss said he had received a tape in the mail with a new version of HSPICE. It included my requested model modification and I was able to continue my development.
The Haileys were remarkable people. Incredibly nice and amazingly brilliant I never met either of them personally but, even though they developed the HSPICE software themselves, they still took the time to speak to and help individual engineering customers if they called. Their achievements are fascinating history. See, for example,http://silicongenesis.stanford.edu/transcripts/hailey.htm.
If I wasn't certain you're already asleep by now, I'd love to relate more of the story of my ancient model!
Task #3: Create a 'Curve-Fit' Capacitance Model
I actually did this once, around-about 1995, as a demo for a presentation at the 1995 Saber Users Group (ASSURE) meeting. I did this using the Saber simulator. I think it took me a few weeks, mostly working at night on my own time. But those files are mostly gone, as far as I can see. So I'd have to start from scratch on this one. Still, this 'old dog' has learned a few new tricks over the years regarding curve-fitting, so it should be a bit easier this time around. Plus I definitely won't have to deal with all the horrible deficits the Saber simulator had then (I'll now use something much more reliable, like LTSpice).
I sort-of remember that MathCad, Excel, and Scientist all gave me the same results for my curve-fit model's capacitances, which agreed well with the device measurements. But when I transferred the exact same formulas to Saber, for some reason which I still don't understand, Saber (and ONLY Saber) gave significantly different results. And I double-checked the formulas I put into Saber many, many times. But, back then, I was pretty much used to having Saber give bogus numerical results under various conditions. I recall that I discovered this and had to investigate it and then extract new parameter values, unique to the Saber model demo, only a few days before the seminar, in order to make the Saber measured/modeled plots agree with measured data. What a pain! For a lot of reasons, and over many years, I learned to not be a big fan of Saber.
Anyway, I've found several curve-fit model versions I built using Scientist and MathCad (both of which I trust). I think I have now found working original application program versions saved on my old PC that will run these model files (but the programs won't even run on my newer PC). I'm not sure which one of the formulas that I still have may be best. But I should be able to develop a curve-fit model, probably for the IRF450R data above, relatively quickly now. I intend to create an LTSpice model using these (or improved) formulas. As usual 'stay tuned'.
Power Mosfet Driver
But this is great news!
For now, I've added a demo plot of my ancient curve fit model at this pageCurve Fit Power MOSFET Capacitance Model. And you can download this simplified model in Excel form (not guaranteed to be useful as a simulator model) at Downloadable Curve Fit Power MOS Capacitance Model Formulas .
Task #4: Create a Physics-Based Capacitance Model
I also did this many years ago, but have lost almost all of the files except the very early attempts at creating this model (well, they're mostly not actually lost, just 'essentially unavailable' to me).
This model was largely physics-based. That is, your input to it was a lot of physical design parameters of the MOSFET such as the drain doping levels (both in the bulk epi but also including a possible surface implant), gate oxide thickness, channel length and width, etc., along with a number of 'curve fitting' parameters to take care of such things as two and three dimensional effects.
That model was designed to be put into the Saber simulator but the project got canceled before that happened (a long and unpleasant story). Anyway, I actually developed the model using MathCad and I still have a few old files from from the early stages of this model development (plus one xerox-ed printout of a somewhat later version). But I'll need to re-read my long, old MathCad output to explain to myself what I knew back then. Plus I'll have to 'finish' it, since this wasn't the final version. Will probably take quite a bit of work, but I really need to do this in order to re-acquaint myself with the MOS theory I knew so long ago. May take many months, as it's a PHD thesis level project, but since I really need to relearn the theory anyway this might actually be the modeling method I tackle first.
Power Mosfet Tutorial
UPDATE 4/3/2013:Because I just found some of my old, partly-finished, 'curve-fit' model formulas (see Curve Fit Power MOSFET Capacitance Model above), I may now try that type of model FIRST as a 'quick gratification' effort. I still really need to 're-learn' my old MOS physics concepts though!
Task #5: Measure and Model Body Diode Soft Reverse Recovery Effects
This task has two major parts, similar to the junction capacitance model development above.
Long ago I developed a power diode soft reverse recovery model enhancement to the existing abrupt-turnoff SPICE diode model (see Advanced Diode Recovery Model ). It used a very simple 'subcircuit' approach, but can yield pretty good results. The same physics that describes the reverse recovery of power diffused junction diodes can also be used to describe most of the effects of reverse recovery of power MOSFET body diodes. So I don't really have any further work to do towards developing a SPICE modeling technique. This is already done.
However, my old modeling techniques are entirely based on measured reverse recovery data. That is, they are curve fits to actual measured waveforms (although there are some physical arguments that can be made that indicate my subcircuit method is compatible with actual device physics). Such reverse recovery measurements require some fairly high speed measurements (often > 100 MHz bandwidth waveforms). Thus they are not particularly easy to do and require a careful test circuit design and fairly high speed test equipment (high power fast pulse generators, fairly high bandwidth scopes, and careful design of diode current measurement techniques). You digital and RF guys just shut up! I know how fast your circuits work these days, but doing (much slower) high power tests can still be challenging.
I expect I won't get to this task for quite a while: tasks #1-4 above are already pretty challenging. A soft reverse recovery model is kind of 'icing on the cake'. But I'll eventually get to it.
I may even have some old 'boatanchor' equipment that is borderline-adequate for doing such measurements (see, for example, an HP 214A Pulse Generator and not-yet described HP54111D or HP 54110D boatanchor digital oscilloscopes). But such a setup will require some pretty careful design and construction, and may not be entirely capable of characterizing all modern fast recovery devices. Will have to try to see!
Task #6: Extend the MOS Models to More Modern Devices (Superjunction and/or GaN and/or SiC Transistors)
My old power MOSFET modeling work is based on the design of the original vertical silicon power DMOS devices. However newer designs such as silicon 'superjunction', GaN, and SiC power MOSFETs have improved characteristics. For superjunction devices the physics is pretty much the same (or, at least, very similar) to the old DMOS designs. GaN and SiC devices may, or may not, operate similarly. But it would be a shame to fail to extend the models for the older-style devices, developed in tasks #1-5 above, towards creating improved models for more modern transistor types.The model formulas may need to be changed a bit to accommodate these device design changes. For example, two and three dimensional 'fudge factors' for a 'superjunction' MOSFET may need to be modified or further enhanced. And, for a physics-based model, the semiconductor parameters (such as bandgap, dielectric constants, etc.) will obviously need to be modified for GaN and SiC devices. In addition, if the new GaN or SiC devices are actually compound devices (I'm aware of at least one GaN product that is a MOSFET/JFET combination) modeling may be difficult or virtually impossible unless the separate devices are also available for individual characterization. This will require further investigation on my part.
And, possibly, the most difficult modeling challenges may be the need to develop lower capacitance/higher switching frequency measurements for the newer devices' characterization. Particularly troublesome for me since I presently have only a VERY limited and VERY old variety of test equipment available.
This 'Task #6' is pretty far down my 'wish list', so it's got to be a longer term goal. But I really want to at least attempt to keep up with technological changes since 1990. However, except for the device measurement/characterization implications, or the possibility of compound devices, this goal may not be quite as difficult as you might think! Please remain somewhat patient, and we'll see what happens!
Copyright © 2013, 2014 Robert Steven Scott